Design and experimental results of a CMOS flip-flop featuring embedded threshold logic
نویسندگان
چکیده
This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we present the concept of flip-flop featuring embedded Threshold Logic, and then we describe the circuit and its operation. Subsequently, we present the design issues and the experimental results of such Threshold Logic flip-flops, obtained in 0.25pm CMOS technology. It is shown in this paper that we successfully manufactured and tested flip-flops having embedded Threshold functions with up to 16 data inputs. The proposed flip-flop featuring embedded Threshold Logic is very suitable for high-performance pipelined arithmetic units since this feature greatly reduces the pipeline overhead, by allowing the elimination of one or more levels of logic from the path leading to the flip-flop.
منابع مشابه
A CMOS flip-flop featuring embedded Threshold logic functions
This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we describe the new Threshold Logic flipflop concept and circuit operation. Second, we present the concepts of embedded Threshold logic and run-time reprogrammability. Finally, it is proved by Spice simulation results that wide (up to 8 inputs) AND/OR Boolean functions can be embedded ...
متن کاملEfficient Timing Element Design Featuring Low Power Vlsi Applications
In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications. Several art of design techniques have been proposed to eliminate large capacitance in the precharge node of the conventional flip-flop, which drives separately by output pull-up, and pull down transistors. Though the pioneer designs which consumes mu...
متن کاملLow Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Using Power Gating Techniques
In this paper, a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFFELM) based on DDFF are introduced. The DDFF offers power and area reduction when compared to the conventional flip-flops. The main aim of DDFF-ELM is to reduce pipeline overhead which arises due to the pipeline setup time, propagation delay and clock skew. It gives an area, power and speed effi...
متن کاملA New Design for Double Edge Triggered Flip-flops
The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other exis...
متن کاملA New Design of Double Edge Triggered Flip-flops
The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1μ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing ...
متن کامل